The RS data sheet (March 1997, component ref. 232-2605; stock no. 302-
003) claims that the device offers automatic leap year compensation. I
wonder what the in-built limits are, given that one of the data sheet
examples refers to 1979, the Econet time ends in 2108, and the NVRAM has
no century flag. How would it know if the year '0' is 1900, 2000, 2100, etc?
Even more complicated, it appears from a cursory look at a disassembly of
the MOS that the FileStore fudges the year value so 0 in the RTC means
1981!
10 Register A (internal function provided by the NVRAM chip)
bit 0 RS0 These four Rate Selection bits select one of the 15 taps on the 22 -stage
divider to select the rate of the square wave on the SQW pin (pin 23, is
connected to TP1) and/or the rate of the periodic interrupt.
The FileStore sets this to provide an output on TP1 at 1.024kHz.
bit 1 RS1
bit 2 RS2
bit 3 RS3
bit 4 DV0 These three DiVider chain bits select what crystal is connected to the
NVRAM. The choice is 4.194304MHz, 1.048576MHz, or 32.768kHz.
The FileStore sets this to 32.768kHz.
bit 5 DV1
bit 6 DV2
bit 7 UIP If set, the RTC cannot be accessed as Update In Progress.
11 Register B (internal function provided by the NVRAM chip)
The FileStore sets these flags to: no DST, 24 hour mode, binary date format,
UIE enable, PIE and AIE both disabled, and clock to not be SET.
bit 0 DSE Daylight Save Enable; may not be available on some 146818s.
bit 1
Select 12 hour or 24 hour mode.
bit 2 DM Is the Date Mode representing binary or BCD format?
bit 3
SQuare Wave Enable, output on pin 23.
bit 4 UIE Update-ended Interrupt Enable (cause IRQ after RTC updated?).
bit 5 AIE Alarm Interrupt Enable (cause IRQ from alarm match).
bit 6 PIE Periodic Interrupt Enable (cause IRQ from periodic timer).
bit 7 SET Inhibit RTC actions so RTC may be set.
12 Register C (internal function provided by the NVRAM chip)
bit 0 not used
bit 1 not used
bit 2 not used
bit 3 not used
bit 4 UF Update-ended interrupt Flag.
bit 5 AF Alarm interrupt Flag.
bit 6 PF Periodic interrupt Flag.
bit 7
IRQ is ours Flag.
13
Register D (internal function provided by the NVRAM chip)
bit 0 not used
bit 1 not used
bit 2 not used
bit 3 not used
bit 4 not used
EEA - FileStore NVRAM allocations
http://angelique/econet/fs/cmos.html
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